A physical limit is imposed on the “shrinking” of such semiconductor structures, i.e. the scaling down of the structure width and the minimum distances between the interconnects. With ever smaller structure widths, the electrical coupling of two tracks running parallel increases drastically. This undesirable parasitic effect leads from performance losses through to functionality failures. In particular, a capacitive coupling between word and bit lines or between two adjacent word lines and thus a signal loss may occur. Even in existing DRAM generations, both effects lead to losses in the circuit speed or to functionality failures (e.g. BLC: Bit Line Coupling).
To date, coupling effects of this type have been compensated for by adapting the design of the semiconductor structure, e.g. by designing the word and bit lines to be shorter. However, this is ultimately connected with a higher area requirement.
It is an object of the invention to reduce the capacitive coupling between adjacent metallic interconnects of a semiconductor structure and thus to make it possible to fabricate a more densely packed semiconductor structure.
This object is achieved according to the invention by means of a semiconductor structure according to claim 1, and a method for fabricating such a semiconductor structure according to claim 4. The subclaims relate to preferred embodiments of the invention.